sv keywords

nand
negedge
new
nexttime
nmos
nor
noshowcancelled
not
notif0
notif1
null
or
output
package
packed
parameter
pmos
posedge
primitive
priority
program
property
protected
pull0
pull1
pulldown
pullup
pulsestyle_ondetect
pulsestyle_onevent
pure
rand
randc
randcase
randsequence
rcmos
real
realtime
ref
reg
reject_on
release
repeat
restrict
return
rnmos
rpmos
rtran
rtranif0
rtranif1
s_always
s_eventually
s_nexttime
s_until
s_until_with
scalared
sequence
shortint
shortreal
showcancelled
signed
small
solve
specify
specparam
static
string
strong
strong0
strong1
struct
super
supply0
supply1
sync_accept_on
sync_reject_on
table
tagged
task
this
throughout
time
timeprecision
timeunit
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
trireg
type
typedef
union
unique
unique0
unsigned
until
until_with
untyped
use
uwire
var
vectored
virtual
void
wait
wait_order
wand
weak
weak0
weak1
while
wildcard
wire
with
within
wor
xnor
xor
accept_on
alias
always
always_comb
always_ff
always_latch
and
assert
assign
assume
automatic
before
begin
bind
bins
binsof
bit
break
buf
bufif0
bufif1
byte
case
casex
casez
cell
chandle
checker
class
clocking
cmos
config
const
constraint
context
continue
cover
covergroup
coverpoint
cross
deassign
default
defparam
design
disable
dist
do
edge
else
end
endcase
endchecker
endclass
endclocking
endconfig
endfunction
endgenerate
endgroup
endinterface
endmodule
endpackage
endprimitive
endprogram
endproperty
endspecify
endsequence
endtable
endtask
enum
event
eventually
expect
export
extends
extern
final
first_match
for
force
foreach
forever
fork
forkjoin
function
generate
genvar
global
highz0
highz1
if
iff
ifnone
ignore_bins
illegal_bins
implies
import
incdir
include
initial
inout
input
inside
instance
int
integer
interface
intersect
join
join_any
join_none
large
let
liblist
library
local
localparam
logic
longint
macromodule
matches
medium
modport
module

x propagation

Very good paper which explains the basic problem related to x propagation (9 pages)
http://www.synopsys.com.cn/edm/2012_lunwen/3/40.pdf

detailed paper
http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf (34 pages)

why synchronous ckts?

Synchronous designs eliminate the problems associated with speed variations

through different paths of logic. By sampling signals at well-defined

time intervals, fast paths and slow paths can be handled in a simple manner.

•

Synchronous designs work well under variations of temperature, voltage and

process. This stability is key for high-volume manufacturing.

•

Many designs must be portable—that is, they must be easy to migrate to a

new and improved technology (say, moving from .6 micron to .35 micron).

The deterministic behavior of synchronous designs makes them much more

straightforward to move to a new technology.

•

Interfacing between two blocks of logic is simplified by defining standardized

synchronous behavior. Asynchronous interfaces demand elaborate handshaking

or token passing to ensure integrity of information; synchronous

designs with known timing characteristics can guarantee correct reception of
data.

Reference:

The Ten Commandments of Excellent Design

Peter Chambers

Engineering Fellow

VLSI Technology

listing all available perl modules

find `perl -e ‘print “@INC”‘ ` -name ‘*.pm’
find -L `perl -e '{printjoin $/, grep {/[^.]/} @INC}’` -name ‘*pm’

Use this command to check wheter the module is installed or not:
perl -e ‘use File::Compare; print “ok\n”‘

Difference between WAND logc and AND logic

Difference between 'wand' and 'and' gates..

 

Some Linux commands

Checking OSname: uname
Checking 64bit or 32bit: getconf LONG_BIT
Processor info:  cat /proc/cpuinfo
Shell type: echo $SHELL

error codes in different simulation tools

Cadence: nchelp
nchelp [options] tool error

Mentor: verror <msgNum>

VCS:

Coding guide lines

Need to finalize this post

General:
http://en.wikipedia.org/wiki/Indent_style
http://geosoft.no/development/cppstyle.html
http://www.gnu.org/prep/standards/standards.html
http://www.mono-project.com/Coding_Guidelines
http://net.tutsplus.com/tutorials/html-css-techniques/top-15-best-practices-for-writing-super-readable-code/

Verilog and System verilog:
http://blogs.mentor.com/nosimulation/blog/2009/09/11/sv-coding-guidelines/
http://blogs.mentor.com/verificationhorizons/
sva : http://www.soccentral.com/results.asp?CatID=488&EntryID=21595

linux file transer

Command for file transfer
scp -r <source file> <dest_user_name>@<dest_host_name>:<dest_path>

GDB

Good sample example for gdb http://www.cs.cmu.edu/~gilpin/tutorial/
http://www.cs.umd.edu/~srhuang/teaching/cmsc212/gdb-tutorial-handout.pdf
gdb cheat sheet  http://users.ece.utexas.edu/~adnan/gdb-refcard.pdf

perl debugging links

http://sunsite.ualberta.ca/Documentation/Misc/perl-5.6.1/pod/perldebtut.html

http://docstore.mik.ua/orelly/perl/prog3/ch20_01.htm

http://www.obsidianrook.com/devnotes/talks/perl_debugger/

frequently used awk

To print first column of a file

awk < file '{print $1}'

To find the sum of first column elements

awk '{total=total+$1} END {print total}' filename

To print all lines sorted by taking 3rd column as reference

awk '{print $3 $0}' < file | sort

awk fields from two different files

 pr -m -t -s\  file1 file2 | gawk '{print $4,$5,$6,$1}'

 

frequently used vi

Frequntly used VI/GVIM commands:

1. Online VI editor: Use this online Vi editor to practice vi commands.

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2. Search and replace:

:%s/searchword/replaceword/  takes care of one occurence of searchword in a line.

:%s/searchword/replaceword/g takes care of all occurences of searchword in a line.

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3. To delete all lines which contains the text "word"

:g/word/d

:g/word1 word2/d

This command tells vi to do a global search for "word word1" and to delete any line containing that text including the space.

-------------------------------------------------------------------------------------------

4. How to indent multiple lines in Vim

• Open up a text file in Vim that needs indenting.
• On the line that you want to start your indenting block type: '=='(This will indent the first line).
• Press the 'v' key to go into visual mode.
• Move the cursor down to select the number of lines you want to indent.
• Press '=' to indent the selected cells.
• As you can see that was the last step, and all your selected lines are indented.

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5. Using vi, you can issue global commands from command mode. If you are not sure of the case used, you can issue this command from vi command mode before you make the global change:

:set ic

(set ignorecase)

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6.

:%s/\'.*$//g

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7. Macros

qa /F_POS_LO <enter> ^i // <ESC> q

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8. To do an operation between two lines
 -------------------------------------------------------------------------------------------

9. vi delete multiline comment

\/\*[a-z0-9A-Z_; ]*\_[a-zA-Z0-9;_ ]*\*\/

:set ic
(set ignorecase) 

revrse a file
tac
tail -r filename

sample verdi argument file

-sv
-2001
-tbbr_debug
+systemverilogext+svh
+incdir+../../../
+incdir+../../../src/
../../../src/ovm_pkg.sv
../../../src/ovm.svh
../utils/utils_pkg.sv
top.sv

special characters in run scripts

If u create a run script in windows and trying to use it in linux, you may see some weird things happening. Problem can be from the special characters that windows use. There are some solutions for this.

1. #include <stdio.h>
main(){
   int i; 
   while((i=getchar())!=EOF)
   if(i=='\t'||i=='\n'||i>=040&&i<=0177) putchar(i);
}
 $ cc temp.c (or whatever you call the above)
 $ a.out < oldfile > newfile

2. Do set list in vi and then remove spcl characters

Beware of waveform viewer

Today, I saw a famous waveform viewer displaying the simulation delta cycles in random order. It is true that simulation tool can take any order while executing different always blocks. But the viewer should not show events in its own random order. Viewer should strictly display the event order taken by the simulator. Application engineer's response was "we got a new version of tool.. please buy/use the latest version."

Controlling event ordering in Questasim

We can control verilog/sv simulation event ordering by using a switch "-noimmedca" with vsim commad. It can avoid false assertion failures because of a particular event ordering.

How to view simulation delta cycles in verdi

1.'setenv NOVAS_FSDB_ENV_DUMP_SEQ_NUM on' in your runscript before simulation.
2. Tools->Event Sequence in nWave window

Questasim

Basic usage:
vlib work //creates work directory
vlog *.sv //compile
vsim -do -pli -sva //run

Questa sim identifies the system verilog files if
1) any file within design contains .sv or .svh or .svp file extension
2) you use -sv argument to vlog command (all files are sv files irrespective of file extension)
3)File extension settings in modelsim.ini (located in install directory)
";SVFileExtensions = sv svp svh"

packed and unpacked randc in class

1 .What is the difference between following classes

class rc1;
randc bit [3:0] rw;
endclass;

class rc2;
randc bit rw [3:0];
endclass;

class rc3;
randc bit [3:0] rw [3:0];
endclass;

rc1 rc1_h=new;
rc1_h.randomize();  //is successfull and rc1_h.rw  has got random value

rc2 rc2_h=new;
rc2_h.randomize();  //is successfull but rc2_h.rw is not getting random value

rc3 rc3_h=new;
rc3_h.randomize();  //is successfull but rc3_h.rw is not getting random value

2. what is the problem in assigning a packed to unpacked (vice versa)?